Memory devices can be designed and manufactured using numerous, different materials and storage techniques. For example, volatile dynamic memory devices are typically fabricated using storage capacitors. Data is stored by changing the capacitor charge, and data is retrieved by sensing the stored charge. Volatile static memory devices are designed using latch circuits to store data, and non-volatile memory devices, such as flash, use floating gate transistors to store data.
Erase operations in a Flash memory device typically start by writing a background of zero to all memory locations in an erase block that are to be erased. This operation is referred to as a Pre-program cycle. Then an erase pulse is applied to the block of memory. A memory state machine, or control circuitry, steps through the array and verifies that all locations are erased. If a location is not erased properly, the state machine applies another pulse and then verifies. The erase pulse application and verification steps are repeated until the block is erased.
A problem can be encountered in some flash memory devices due to excessive amounts of current that are drawn during the initial pulses of an erase operation. One technique used to erase memory cells is to apply a positive voltage to the source of the cells and a negative voltage to the control gate of the cells. The negative voltage on the gate further couples negatively an already programmed floating gate of the cell. A tunnel current is formed between the source to the floating gate due to the electric field, and a Gate Induced Drain Leakage current (GIDL). This current is a result of gate diode breakdown of the cell because the floating gate cell has a big negative voltage and the source has a large positive voltage. The electric field in the gate to source area causes a breakdown in the depletion region, which sends some of the current to the memory substrate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved erase circuitry for non-volatile memory devices.